1. Field of the Invention
The present invention relates to a memory system including at least one memory device and a memory controller adapted to control operation of the memory device.
2. Description of the Related Art
In conventional DRAM memory systems for writing data into a DRAM device and for reading out data from the DRAM device, different clock signals are provided wherein the write clock is generated within the memory controller and the read clock is generated within the memory device. Usually both the write clock and the read clock are independent from each other, supplied via different clock lines and provided to different clock inputs at the memory device.
In future high-speed memory interfaces, e.g., in view of DDR-4 (Double Data Rate) the pin count for each channel of the memory device increases substantially, e.g., due to the introduction of a differential signalling. In such a memory system, the clock signals will be provided by at least three lines, e.g., one clock line for transmitting command and address signals, one write clock which is synchronized with data to be written and one read clock which is synchronized with data to be read out of the memory device. The high pin count results in an increased power consumption and renders the design of the memory system more complex.
It is therefore an aspect of the present invention to reduce the interconnection lines within a memory system and more particularly, to reduce the pin count of a memory device used in such a memory system.